Low-Power built-in logic block observer realization for BIST applications

This paper presents a low-power built-in logic block observer (LP-BILBO) to realize the performance in minimum power consumption. The proposed LP-BILBO is based on a low-power test module (LPTM) design to divide the system clock into two independent clocks for reducing the switching activity in power savings. Simulation results show that the proposed LP-BILBO can effectively save its own power consumption up to 48% (on average) during the low-power operation modes. Also, the performance analysis in benchmark ISCAS´89 circuits indicates that on average 44% power reduction can be obtained when the proposed LP-BILBO is adopted in the testing scheme.