A true off-set self-aligned process for high efficiency Ku-band power FETs

A novel offset self-aligned process has been used to fabricate an internally matched power FET with a 2-*3000- mu m gate width which at 14 GHz has produced 34.4-dBm output power, 6-dB gain, and 32% power-added efficiency at the -1 dB gain compression point with a power combining efficiency of approximately=96%. The high combining efficiency is attributed to the close parameter match of the self-aligned power FETs. In this process, the source, gate, and drain openings are defined simultaneously. The source-gate self-alignment permits a relatively shallow gate recess (0-600 AA), which preserves the uniformity of the active layer. The self-aligned gate-drain spacing results in a large and uniform gate-drain breakdown voltage which is especially important for power applications.<>