Hardware/software co-verification scheme for MSTP ASIC

To verify the functions of the MSTP ASIC designed by our research group, a feasible hardware/software co-verification scheme is proposed in this paper. The scheme includes integrated hardware/software and detailed testing procedure for all available patterns of the chip. The testing process is divided into two steps: the loop testing which can be easily built without additional devices; and the functional and performance testing which can completely check the chip´s functions. This scheme provides a highly efficient low-cost way of testing ASICs of the similar type. Moreover, we have implemented the whole testing scheme on a highly integrated hardware platform and successfully verified our MSTP ASIC.