Title :
A 6b 600MS/s 5.3mW Asynchronous ADC in 0.13/spl mu/m CMOS
Author :
Chen, Shuo-Wei Mike ; Brodersen, Robert W.
Author_Institution :
California Univ., Berkeley, CA
Abstract :
A 1.2V 6b ADC using asynchronous processing with dual time interleaving and non-binary successive approximation achieves 600MS/s while dissipating 5.3mW in a 0.13mum CMOS process. A capacitive ladder network is used to reduce the input capacitance without compromising matching accuracy. The ADC occupies an active area of 0.12mm2 and has an input 3dB BW of over 4GHz
Keywords :
CMOS integrated circuits; analogue-digital conversion; asynchronous circuits; ladder networks; 0.13 micron; 1.2 V; 5.3 mW; 6 bit; CMOS process; asynchronous analog-to-digital converter; capacitive ladder network; CMOS technology; Capacitors; Circuits; Clocks; Energy consumption; Energy resolution; Latches; Preamplifiers; Sampling methods; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0079-1
DOI :
10.1109/ISSCC.2006.1696298
