DocumentCode :
2571134
Title :
A 1GS/s 11b Time-Interleaved ADC in 0.13/spl mu/m CMOS
Author :
Gupta, Sandeep ; Choi, Michael ; Inerfield, Michael ; Wang, Jingbo
Author_Institution :
Teranetics Inc., Santa Clara, CA
fYear :
2006
fDate :
6-9 Feb. 2006
Firstpage :
2360
Lastpage :
2369
Abstract :
A time-interleaved ADC architecture that eliminates the need to correct timing offsets and is scalable to high sampling rates is presented. This 1GS/S 11b ADC has 55dB peak SNDR, consumes 250mW power, and occupies 3.5mm2 area
Keywords :
CMOS integrated circuits; analogue-digital conversion; 0.13 micron; 11 bit; 250 mW; ADC architecture; CMOS integrated circuits; analog-to-digital converters; sampling rates; timing offsets; Bandwidth; Circuits; Clocks; Error correction; Linearity; Sampling methods; Signal processing; Signal sampling; Switches; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
ISSN :
0193-6530
Print_ISBN :
1-4244-0079-1
Type :
conf
DOI :
10.1109/ISSCC.2006.1696299
Filename :
1696299
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2571134
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