A design approach for predictable and efficient multi-core processor for avionics

Academic Predictable Multi-core Processor: MERASA & PRET processors COTS architecture: IBM™ Cell, Freescale™´s MPC8641D & QorIQ Platform Local memories (scratchpads & caches): • Best cache policy (for analyzability) • Cache Analysis (optimization to reduce cache pollution) • Shared Cache Strategy to reduce interferences Interconnect Element: • Shared Bus (bounding access time) • Ring protocols • CoreNet, & Data Path Accelerator Architecture