Experiments on reducing standby current for compilable SRAM using hidden clustered source line control

This work develops a hidden clustered source line control (HCSLC) technique to reduce the standby current of an embedded SRAM with zero area overhead. The HCSLC scheme utilizes meshed multiple source line control to reduce the fluctuations of virtual ground voltages that are caused by IR drops and process variations. A clustered device-hidden layout scheme is employed to produce compact SRAM layout and attenuate the effects of location/direction-dependent process variations on source line control circuits. A 512 Kb HCSLC SRAM testchip was fabricated using the 0.18 um CMOS process. The HCSLC SRAM achieves 69%~77% reductions of standby current for various processes, supply voltages and temperatures (PVT). The data retention voltage in sleep mode is 0.1 V~0.15 V higher than that in normal mode for the HCSLC SRAM.