Thermal-aware incremental floorplanning for 3D ICs

Three dimensional integrated circuits (3 D ICs) are introduced as one way to address the bottlenecks from interconnect delays in sub-micro VLSI design. Despite their advantages over traditional 2 D ICs, the heat dissipation has become an extremely important issue in 3 D ICs. In this paper, a novel thermal-driven 3 D incremental floorplanning algorithm is proposed using the mixed integer linear programming (MILP) formulation. With our analytical approach, chip-area, wirelength and maximal on-chip temperature could be optimized simultaneously. Additionally, by the iterative modification flow, we can improve the packing result incrementally. Experimental results show that compared to the original floorplans, our incremental floorplans could reduce max on-chip temperature by about 27 % while chip area and total wirelength are enlarged just 1 % and 2 %, respectively.