Low-Temperature Monolithic Three-Layer 3-D Process for FPGA

We developed a wafer-scale, monolithic, 3-D integrated circuit process that features three active layers: a silicon base layer with CMOS circuitry, a second layer of germanium (Ge) PMOS devices, and a top layer of AlOxNy resistive random access memory (RRAM) cells. The temperatures of all processes, following the fabrication of the CMOS circuitry, are below 400°C to ensure no damage to the CMOS circuitry. The Ge layer is applied as an array of islands using low-temperature aligned bonding, followed by cleaving at the buried layer of implanted hydrogen ions. The Ge PMOS devices are lithographically aligned to the underlying CMOS and feature metal gates over high-κ dielectric. The RRAM devices built into the third layer exhibit sub-μA switched currents. This process is attractive for a compact field-programmable gate array with reduced area, delay, and power.