• DocumentCode
    2571521
  • Title

    Local refinement method for optimizing clock tree topology

  • Author

    Fu, Qiang ; Luk, Wai-Shing ; Zhao, Wenqing ; Chen, Shijun ; Zeng, Xuan

  • Author_Institution
    Fudan Univ., Shanghai
  • fYear
    2007
  • fDate
    22-25 Oct. 2007
  • Firstpage
    1110
  • Lastpage
    1113
  • Abstract
    An effective method that incorporates with the Deferred-Merge Embedding algorithm is presented for clock tree construction. To achieve better performance, a sequence of tree topologies are generated by a local refinement technique. Three types of local perturbations are considered, namely swapping, tree rotation and H-flip. To speedup the proposed method, incremental cost updating is used. Experimental results show that total wirelength could be reduced effectively around 10% under Elmore delay model.
  • Keywords
    circuit optimisation; clocks; integrated circuit design; network topology; Elmore delay model; H-flip; clock tree construction; clock tree topology; deferred-merge embedding; incremental cost updating; integrated circuit design; local refinement; tree rotation; Application specific integrated circuits; Clocks; Costs; Educational programs; Joining processes; Optimization methods; Partitioning algorithms; Simulated annealing; Topology; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC, 2007. ASICON '07. 7th International Conference on
  • Conference_Location
    Guilin
  • Print_ISBN
    978-1-4244-1132-0
  • Electronic_ISBN
    978-1-4244-1132-0
  • Type

    conf

  • DOI
    10.1109/ICASIC.2007.4415827
  • Filename
    4415827