A sub-1.5/spl deg/ /sub rms/ Phase-Noise Ring-Oscillator-Based Frequency Synthesizer for Low-IF Single-Chip DBS Satellite Tuner-Demodulator SoC

Author

Maxim, A. ; Poorfard, R. ; Kao, J.

Author_Institution

Silicon Labs., Austin, TX

fYear

2006

fDate

6-9 Feb. 2006

Firstpage

2552

Lastpage

2561

Abstract

A fully integrated 0.13mum CMOS ring-oscillator-based PLL for low-IF single-chip DBS satellite tuner-demodulator IC is presented. A noise-attenuating loop filter reduces the oscillator gain, helping both front-end noise and spur rejection and allowing the on-chip integration of the filter capacitance. The PLL shows <1.5deg_rms double-sided integrated phase noise, <-60dBc reference spurs, <-50dBc coupled spurs. It occupies 0.3mm² die area and consumes 40mA at 3.3V

Keywords

CMOS integrated circuits; frequency synthesizers; oscillators; phase locked loops; phase noise; system-on-chip; 0.13 micron; 3.3 V; 40 mA; CMOS ring-oscillator-based PLL; DBS satellite system-on-chip; filter capacitance; noise-attenuating loop filter; phase locked loop; phase noise; ring-oscillator-based frequency synthesizer; tuner-demodulator system-on-chip; CMOS integrated circuits; Capacitance; Filters; Frequency synthesizers; Integrated circuit noise; Noise reduction; Oscillators; Phase locked loops; Satellite broadcasting; Tuners;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

1-4244-0079-1

Type

conf

DOI

10.1109/ISSCC.2006.1696320

Filename

1696320