• DocumentCode
    2571562
  • Title

    A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor

  • Author

    Davis, J. ; Plass, Donald ; Bunce, P. ; Chan, Yan-Cheong ; Pelella, A. ; Joshi, Rajan ; Chen, Aaron ; Huott, W. ; Knips, T. ; Patel, Pragati ; Lo, Kuo-Hua ; Fluhr, E.

  • Author_Institution
    IBM, Poughkeepsie, NY
  • fYear
    2006
  • fDate
    6-9 Feb. 2006
  • Firstpage
    2564
  • Lastpage
    2571
  • Abstract
    A dual-read 8-way set-associative data cache comprising four 16kB SRAMs and 2 set-prediction macros per P0WER6 core is presented. The array utilizes a 0.75mum2 butted-junction split-word line 6T cell in 65nm SOI. The design features dual power supplies, unidirectional polysilicon, and hierarchical undamped bit lines for enhanced cell stability and performance
  • Keywords
    SRAM chips; cache storage; microprocessor chips; silicon-on-insulator; 5.6 GHz; 65 kBytes; POWER6 processor; SRAM; dual power supplies; dual-read data cache; set-associative data cache; silicon-on-insulator; unidirectional polysilicon; Circuits; Clocks; Decoding; MOS devices; Microprocessors; Pipelines; Random access memory; Signal generators; Stability; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    1-4244-0079-1
  • Type

    conf

  • DOI
    10.1109/ISSCC.2006.1696322
  • Filename
    1696322
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2571562