Parametric analysis of multiple interconnects via canonical reduced order modeling

For design nodes at 65 nm and below, timing will essentially be a statistical measure of the fabricated circuit and heavily correlated with process variation. This paper proposes a novel parametric interconnect analysis using canonical reduced order modeling. Models in canonical forms have the feature of a small number of free model parameters. This property can be made use of effectively for parametric analysis via interpolation. Experimental results demonstrate the effectiveness of the proposed methodology.