DocumentCode
2571620
Title
A 256kb Sub-threshold SRAM in 65nm CMOS
Author
Calhoun, Benton H. ; Chandrakasan, Anantha
Author_Institution
Massachusetts Inst. of Technol., Cambridge, MA
fYear
2006
fDate
6-9 Feb. 2006
Firstpage
2592
Lastpage
2601
Abstract
A 256kb sub-threshold SRAM operates below 400mV from 0 to 85degC and is implemented in 65nm CMOS technology. For the same 6sigma static-noise margin, the sub-threshold SRAM at 0.4V achieves 2.25-times lower leakage power and 2.25-times lower active energy than its 6T counterpart at 0.6V. The SRAM uses a 10T bitcell to enable sub-threshold functionality
Keywords
CMOS memory circuits; SRAM chips; integrated circuit design; low-power electronics; 0 to 85 C; 0.4 V; 0.6 V; 256 kBytes; 65 nm; CMOS integrated circuit; leakage power; static-noise margin; sub-threshold SRAM; sub-threshold functionality; Buffer storage; CMOS logic circuits; CMOS technology; Degradation; Inverters; Leakage current; Low voltage; Random access memory; Region 3; Stability;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
1-4244-0079-1
Type
conf
DOI
10.1109/ISSCC.2006.1696325
Filename
1696325
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