Title :
Redefinition of Write Margin for Next-Generation SRAM and Write-Margin Monitoring Circuit
Author :
Takeda, Koichi ; Ikeda, Hidetoshi ; Hagihara, Yasuhiko ; Nomura, Masahiro ; Kobatake, Hiroyuki
Author_Institution :
NEC, Sagamihara
Abstract :
We redefine write margin in order to be able to quantify the effect of both PVT variation and write-margin improvement. A write-margin monitoring circuit based on this definition is implemented in a 90nm CMOS process. This circuit can be applied to an SRAM power supply circuit to improve the write margin
Keywords :
CMOS memory circuits; SRAM chips; power supply circuits; 90 nm; CMOS process; PVT variation; SRAM power supply circuit; next-generation SRAM; write margin redefinition; write-margin monitoring circuit; Circuits; Inverters; MOSFETs; Monitoring; National electric code; Performance evaluation; Random access memory; Temperature; Testing; Threshold voltage;
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0079-1
DOI :
10.1109/ISSCC.2006.1696326
