Threshold voltage modeling of deep-submicron double-gate fully-depleted SOI MOSFET

In this paper, the threshold voltage model using a quasi -2D approximation for deep submicron double-gate fully-depleted SOI PMOS devices was described by solving basic semiconductor physical equations. Taking into consideration the distribution of minority carriers in the silicon film, the analytical threshold voltage model to make an accurate prediction of short-channel effect has been obtained, and also a further threshold voltage model including DIBL effect and interface charge effect was obtained. The analytical voltage model applies also to SOI NMOS devices. All of the above models have been verified by the results of 2D device simulator MEDICI.