An efficient preconditioning scheme for fast hierarchical method in 3-D capacitance extraction of IC interconnect

With technology shrinking, the interconnect effect has been a key challenge to improve the IC performance. The swift and accurate 3-D capacitance extraction plays a significant role in the VLSI design and verification. For exactly extracting the 3-D capacitance, numerical solution of the integral equations is entailed. Fast hierarchical method (FHM) has been proven to be an efficient acceleration algorithm for three-dimensional (3-D) capacitance extraction. In the FHM, however, the conventional preconditioning techniques for an explicit matrix are not applicable since no coefficient matrix is actually constructed. In this work, a preconditioning technique for the FHM is proposed by carefully examining inherent properties of the hierarchical data structure in the FHM. This preconditioning technique significantly enhances convergence of the iterative solution yet preserves the implicit nature of the matrix operations in the FHM.