DocumentCode
2571917
Title
The cycle accurate DSP model design based on SystemC
Author
Dai, Lin ; Liu, Zhenyao
Author_Institution
Southeast Univ., Nanjing
fYear
2007
fDate
22-25 Oct. 2007
Firstpage
1201
Lastpage
1204
Abstract
With the development of the DSP design technique, the DSP structure becomes more and more complex and the speed of RTL simulation is slower and slower. In this paper, a cycle accurate DSP model based on SystemC is designed to speed up the simulation. Through the simulation of g.721 audio encoding program and the IDCT that is the main part of image processing, the time of cycle accurate DSP model simulation is about one minute and ten seconds, however the time of RTL simulation is about thirty minutes and five minutes.
Keywords
digital signal processing chips; network synthesis; IDCT; SystemC; audio encoding program; cycle accurate DSP model design; image processing; Analytical models; Application specific integrated circuits; Automata; Clocks; Design engineering; Digital signal processing; Hardware; Signal analysis; Timing; Yarn;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2007. ASICON '07. 7th International Conference on
Conference_Location
Guilin
Print_ISBN
978-1-4244-1132-0
Electronic_ISBN
978-1-4244-1132-0
Type
conf
DOI
10.1109/ICASIC.2007.4415850
Filename
4415850
Link To Document