VLSI implementation of reconfigurable SRRC filters with automatic code generation

A novel way to realize Square Root Raised Cosine (SRRC) filters with different taps, different accuracies and fixed architecture is proposed in this paper. An automatic code generation method is introduced because the architecture adopted in this paper is regular. In this way, both the number of the taps and Canonic Signed Digit (CSD) code´s bit width are reconfigurable, and a variety of filters with fixed structure and different taps and accuracies can be realized efficiently. The synthesis result shows that a 257-tap SRRC filter using the architecture suggested in this paper can operate at a maximum frequency of 168.9 MHz with a cost of 86135 equivalent gates.