Complexity reduction for SOPC-based H.264/AVC coder via sum of absolute difference

There exist a number of complex encoding techniques which make H.264 video coding much more efficient, such as the adoption of variable block sizes, multiple reference frames, and the consideration of rate-distortion optimization (RDO). However, these techniques come with a price, i.e. considerable increase of complexity due to the introduction of motion estimation (ME) and mode decision in the design of H.264. In this paper, we have proposed a cost-effective complexity reducing coding algorithm for removing H.264 ME redundancy in SOPC-based embedded systems. The loosely coupled accelerators for Avalon switch fabric compliant topology reveal that the potential coder design can achieve the advantages of flexibility and performance in circuit design without incurring much of the design risk.