Fabrication method for IC-oriented Si twin island single electron transistors

Author

Ono, Y. ; Takahashi, Y. ; Yamazaki, M. ; Nagase, M. ; Namatsu, H. ; Kurihara, K. ; Murase, K.

Author_Institution

NTT Basic Res. Labs., Atsugi, Japan

fYear

1998

fDate

6-9 Dec. 1998

Firstpage

123

Lastpage

126

Abstract

A new fabrication method for Si single-electron transistors (SETs) is proposed. The method enables us to fabricate, in a self-aligned way, a twin-island SET in which two Si islands are aligned in parallel. Experimental devices demonstrated, at 40 K, that the twin-island SET structure can be operated as two individual SETs. Since the two SETs are packed in a tiny area, this method is suitable for constructing logic circuits based on pass-transistor-type logic and CMOS-type logic, which promises to lead to single-electron logic LSIs.

Keywords

CMOS logic circuits; elemental semiconductors; large scale integration; oxidation; silicon; single electron transistors; 40 K; CMOS-type logic; Si; fabrication method; logic LSIs; logic circuits; pass-transistor-type logic; self-aligned technique; twin island single electron transistors; Capacitance; Electrodes; Equivalent circuits; Etching; Fabrication; Joining processes; Oxidation; Single electron transistors; Stress; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-4774-9

Type

conf

DOI

10.1109/IEDM.1998.746294

Filename

746294