• DocumentCode
    2572490
  • Title

    Accelerating system performance using SOPC builder

  • Author

    Dalay, B.

  • Author_Institution
    Senior Product Marketing Engineer
  • fYear
    2003
  • fDate
    19-21 Nov. 2003
  • Firstpage
    3
  • Lastpage
    5
  • Abstract
    The availability of multi million-gate FPGA devices has opened the possibility to create complex single chip systems that were previously partitioned into discrete devices and boards. This paper describes the tools and methods to create these designs. It is shown that the ability of the integration tools that are available to today enable the designer to move away from the traditional flow of creating an over specified hardware base and fixing the system by applying creativity to the software. Exact fit solutions that are more economic to produce are made possible with the additional levels of performance enhancement granularity that is available to systems portioning that is afforded by the additional flexibility.
  • Keywords
    circuit optimisation; field programmable gate arrays; hardware description languages; system-on-chip; SOPC builder; discrete devices; hardware base; integration tools; multimillion-gate FPGA devices; performance enhancement granularity; single chip systems; system performance; Acceleration; Automatic logic units; Europe; Field programmable gate arrays; Graphical user interfaces; Hardware design languages; Master-slave; Programming; Software design; System performance;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    System-on-Chip, 2003. Proceedings. International Symposium on
  • Print_ISBN
    0-7803-8160-2
  • Type

    conf

  • DOI
    10.1109/ISSOC.2003.1267702
  • Filename
    1267702