Statistical worstcase interconnect modeling based on non-normal distributed process variations for nanometer era

In this paper, we propose a new statistically-based approach for the characterization of the realistic worstcase interconnect models. In order to extract optimized parameters consistently in the worstcase simulation and to solve the non-normal distribution problems that were treated as normal distributions in the previous methods, the effective common geometry (ECG) and accumulated maximum probability (AMP) algorithms have been developed and implemented into the new statistical worstcase interconnect design environment. The delay time of the 31-stage ring oscillator that is manufactured in UMC 0.13 mum logic and 15-stage ring oscillator in 0.18 mum standard CMOS process was measured. When the algorithms were used to determine the worstcase, it was two times more accurate with the relative error less than 1.00% than that of the conventional Monte Carlo method (MCM). The new worstcase interconnect design environment improved the optimization speed by 32.01% compared to that of the conventional worstcase optimizer. The new worstcase interconnect design environment fast and accurately predicted the worstcase/bestcase of the non-normal distribution which conventional methods cannot do very well.