DocumentCode :
2572514
Title :
Hardware acceleration for sparse fourier image reconstruction
Author :
Dinh, Quang ; Bresler, Yoram ; Chen, Deming
Author_Institution :
Univ. of Illinois at Urbana Champaign, Urbana Champaign
fYear :
2007
fDate :
22-25 Oct. 2007
Firstpage :
1346
Lastpage :
1351
Abstract :
Several supercomputer vendors now offer reconfigurable computing (RC) systems, combining general-purpose processors with fie Id-program m able gate arrays (FPGAs). The FPGAs can be configured as custom computing architectures for the computationally intensive parts of each application. In this paper we present an RC-based hardware accelerator for an important medical imaging algorithm: iterative sparse Fourier image reconstruction. We transform the algorithm to exploit massive parallelism available in the FPGA fabric. Our design allows different ways of chaining custom pipelined vector engines, so that different computations can be carried out without reconfiguration overhead. Actual runtime performance data show that we achieve up to 10 times speedup compared to the software-only version. The design is estimated to provide even more speedup on a next-generation RC platform.
Keywords :
Fourier transforms; field programmable gate arrays; image reconstruction; medical image processing; FPGA; RC-based hardware accelerator; fieId-programmable gate arrays; hardware acceleration; medical imaging algorithm; reconfigurable computing systems; sparse Fourier image reconstruction; Acceleration; Biomedical imaging; Computer architecture; Fabrics; Field programmable gate arrays; Hardware; Image reconstruction; Iterative algorithms; Parallel processing; Supercomputers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC, 2007. ASICON '07. 7th International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4244-1132-0
Electronic_ISBN :
978-1-4244-1132-0
Type :
conf
DOI :
10.1109/ICASIC.2007.4415887
Filename :
4415887
Link To Document :
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