CTL based DFT solution to accelerate design to test development for system on chip devices

In this presentation, we will explain how CTL has been designed as a very rich and powerful language that can be leveraged in a DFT solution. While CTL has been designed with the primary focus of communicating information between the core providers and the SoC test integrators, it is showing very useful as a communication mechanism form the EDA world to the ATE. CTL does not only support cores tested with the standard scan approach; IP blocks with embedded logic BIST and memories can also be described in CTL. An EDA DFT solution based on CTL enables full automation of scan and BIST at the core level and test integration at the SoC level.