Word parallelism vs spatial parallelism: a performance optimization technique on the PAPRICA system

Starting from the analysis of the hardware efficiency of SIMD systems which use an external memory for data storage, this paper discusses a critical point in hardware design. In particular it presents a technique aimed to the maximization of the data bus efficiency. This technique is based on the transformation of the initial data set into a packed one, and can be successfully implemented on systems which allow a dynamic mapping between the processing array and the external memory. As an example, the PAPRICA system is considered. An optimizing assembly-to-assembly translator has been developed for the automatic conversion of a generic PAPRICA assembly program working on binary data sets into its equivalent version working on packed data sets. An, example of a thinning filter shows how this technique can improve the performances