DocumentCode
2572976
Title
Mappability estimate: a measure of the goodness of a processor-algorithm pair
Author
Kreku, J. ; Soininen, Juha-Pekka
Author_Institution
VTT Electron., Oulu, Finland
fYear
2003
fDate
19-21 Nov. 2003
Firstpage
119
Lastpage
122
Abstract
A quick way of measuring the goodness of a processor-algorithm pair is presented. The main emphasis in this paper is in the reasoning of the mappability factors of a processor and an algorithm. Typical algorithm properties and how they affect the usability of the corresponding architecture characteristics are considered. The mappability estimation approach is demonstrated using MiBench benchmark algorithms and the Simplescalar processor simulator with ARM instruction set. The estimation results are consistent with the simulations and the estimates correctly predicted the most suitable architectures for three of the four algorithms.
Keywords
algorithm theory; circuit simulation; estimation theory; hardware-software codesign; instruction sets; system-on-chip; ARM instruction set; MiBench benchmark algorithms; Simplescalar processor simulator; algorithm properties; architecture characteristics; mappability estimate; mappability factors; processor-algorithm pair; Clocks; Computational modeling; Computer architecture; Computer networks; Costs; Information analysis; Predictive models; Resource management; Silicon; Usability;
fLanguage
English
Publisher
ieee
Conference_Titel
System-on-Chip, 2003. Proceedings. International Symposium on
Print_ISBN
0-7803-8160-2
Type
conf
DOI
10.1109/ISSOC.2003.1267731
Filename
1267731
Link To Document