A system level IP integration methodology for fast SOC design

In the system-on-chip (SOC) era, the growing number of functionalities included on a single chip requires the development of new design methodologies to keep the design complexity under control. Intellectual property reuse has been commonly employed as a technique to address this problem, but a new system-level approach is needed to integrated IP-reuse methodology in the design flow, in order to speed up the designer´s productivity. In this paper, a SOC design platform is proposed as a solution to this problem, providing a library of IP reusable blocks and a high level tool for SOC design development. An IP library based on AMBA bus architecture was built, featuring a collection of devices with homogeneous interfaces described with VHDL language constructs that enable hardware configurability. A system-level assembler (SLA) was then developed to provide a hardware configuration tool and a suite of utilities to support the designer work. Once defined the system structure, the SLA allows automatic generation of the environments used for software development, simulation, synthesis and verification tasks.