Functional high-speed characterization and modeling of a six-layer copper wiring structure and performance comparison with aluminum on-chip interconnections

Experimental high-speed characterization and electrical modeling and simulation are presented for a six-layer Cu/SiO/sub 2/ on-chip wiring structure with 12.4-mm-long lines. Testing is performed over the temperature range -160/spl deg/C to +100/spl deg/C and across a 200-mm-diameter wafer. Very good agreement is reported between measured and simulated signal propagation and crosstalk waveforms. Modeling is done using a three-dimensional field solver and the R(f), L(f), and C matrices are used in a synthesized distributed network to simulate the signal behavior. Such a broadband analysis comprises the first comprehensive functional testing of a multi-layer Cu/SiO/sub 2/ wiring structure. The Cu interconnections are shown to be able to sustain 5.39 GHz microprocessor frequencies at T=+25/spl deg/C operation at a scaled wiring density increase of 17.5%, while comparable Al(Cu) wiring can achieve only 4.44 GHz (21.4% improvement).