Design of a parametrizable low cost Ethernet MAC core for SoC solutions

Author

Zamora, José Antonio Moreno ; Corrales, Pedro Jose Rodriguez ; Pérez, Juan Manuel Sánchez

Author_Institution

Dept. of Electron., Extremadura Univ., Badajoz, Spain

fYear

2003

fDate

19-21 Nov. 2003

Firstpage

139

Lastpage

142

Abstract

This paper describes an efficient Ethernet medium access control (MAC) design, according to IEEE 802.3 standards for fast Ethernet (100 Mbps) a 10Base-T (10 Mbps) implementations in full and half duplex modes, suitable for re-use as intellectual property (IP) core in system-on-chip (SoC) designs. The description and contributed results exhibit that the main advantages of this design reside in a really low logic cost keeping a great tolerance for external clock frequencies and domains, and a high configurability and flexibility for master processors interface.

Keywords

IEEE standards; access protocols; integrated circuit design; local area networks; logic design; system-on-chip; 10 Mbit/s; 100 Mbit/s; 10Base-T implementations; Ethernet medium access control; IEEE 802.3; IP core; MAC design; SoC designs; SoC solutions; fast Ethernet; full duplex modes; half duplex modes; intellectual property reuse; master processors interface; parametrizable Ethernet MAC core; system-on-chip design; Bandwidth; Clocks; Costs; Ethernet networks; Field programmable gate arrays; Frequency synchronization; Logic design; Media Access Protocol; Network topology; Physical layer;

fLanguage

English

Publisher

ieee

Conference_Titel

System-on-Chip, 2003. Proceedings. International Symposium on

Print_ISBN

0-7803-8160-2

Type

conf

DOI

10.1109/ISSOC.2003.1267737

Filename

1267737