Lookback BiST for RF front-ends in digital transceivers

This paper addresses a built-in self-test (BiST) for ICs digital transceivers. The focus is on testing the RF front-end while taking advantage of the on-chip DSP resources and DA-, and AD converters. The loopback architecture is used to preserve the sensitive RF blocks from extra noise and external disturbances. The test aims at spot defects typical of RF CMOS ICs, where those faults are deemed the main yield limiter in mass production. The fault model is discussed at three levels of design abstraction: layout, circuit and functional block. The BiST model is verified at the circuit and functional level. As a demonstrator a GSM transceiver model with loopback BiST is presented that provides a promising result.