Evaluation of fully-integrated switching regulators for CMOS process technologies

Author

Lee, Jaeseo ; Hatcher, Geoff ; Vandenbergh, Lieven ; Yang, Chih-Kong Ken

Author_Institution

California Univ., Los Angeles, CA, USA

fYear

2003

fDate

21-21 Nov. 2003

Firstpage

155

Lastpage

158

Abstract

In this paper, we examine the feasibility of fully integrated voltage regulator for the power-optimized system-on-chip (SoC). The challenges and tradeoffs in designing fully-integrated buck switching regulators in CMOS process are described and a compact macro-power-model of a regulator is created. Optimization using geometric programming finds the optimal active and passive device sizes of on-chip regulator for highest efficiency in current and future process technologies. A fully-integrated switching regulator is designed and fabricated in a 0.35-mum CMOS process to validate our modeling. The model is extrapolated to emerging CMOS technologies to show that >70% efficiency is possible.

Keywords

CMOS integrated circuits; geometric programming; integrated circuit design; integrated circuit modelling; switching convertors; voltage regulators; 0.35 microns; CMOS process technologies; SoC; buck switching regulators; geometric programming; macropower model; on-chip regulator; optimal active device size; optimal passive device sizes; power-optimized system-on-chip; voltage regulator; Buck converters; CMOS process; CMOS technology; Design optimization; Inductors; Regulators; Semiconductor device modeling; Switching frequency; System-on-a-chip; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

System-on-Chip, 2003. Proceedings. International Symposium on

Conference_Location

Tampere

Print_ISBN

0-7803-8160-2

Type

conf

DOI

10.1109/ISSOC.2003.1267744

Filename

1267744