DocumentCode :
2573183
Title :
A Brief Implementation Analysis of SHA-1 on FPGAs, GPUs and Cell Processors
Author :
Zhou, Lin ; Han, Wenbao
Author_Institution :
Dept. of Appl. Math., Zhengzhou Inf. Eng. Univ., Zhengzhou, China
fYear :
2009
fDate :
2-3 May 2009
Firstpage :
101
Lastpage :
104
Abstract :
Recently, there has been much discussion about new advancements in processor technology that promise huge performance returns for a small investment in cryptography. Field programmable gate arrays (FPGAs), cell processors and graphics processor units (GPUs) are all the rage. We investigate the implementation and performance of SHA-1 using them, with the view of comparison their salient features. Our results shows that the implementation on FPGA could achieve the smallest performance-to-price ratio. But it cost lowest energy, had the smallest area and very stable.GUPspsila performance-to-price ratio is biggest. But its power is very big around 400-600 W and less stable. We can get almost of throughput of GPU using cell Processors and used less power than GPU around 135 W. But its price is higher than GPUs.
Keywords :
cryptography; field programmable gate arrays; microprocessor chips; FPGA; SHA-1; cell processors; cryptography; field programmable gate arrays; graphics processor units; Arithmetic; Bandwidth; Cryptography; Field programmable gate arrays; Graphics; Hardware; Mathematics; Performance analysis; Signal processing algorithms; Software performance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Engineering Computation, 2009. ICEC '09. International Conference on
Conference_Location :
Hong Kong
Print_ISBN :
978-0-7695-3655-2
Type :
conf
DOI :
10.1109/ICEC.2009.11
Filename :
5167101
Link To Document :
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