Title :
Multiple-thickness gate oxide and dual-gate technologies for high-performance logic-embedded DRAMs
Author :
Togo, M. ; Noda, K. ; Tanigawa, T.
Author_Institution :
ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan
Abstract :
We demonstrate new fabrication technologies for dual-gate CMOSFETs with multiple-thickness gate oxide. The process consists of two major parts: forming a multiple-thickness gate oxide by using Ar/sup +/ and N/sup +/ implantation, and impurity doping into dual-gate poly-Si by using self-aligned thermal oxidation. During the doping process, nitrogen distribution recoiling from a Si/sub 3/N/sub 4/ on a PMOSFET gate suppresses boron penetration.
Keywords :
DRAM chips; application specific integrated circuits; argon; elemental semiconductors; ion implantation; nitrogen; oxidation; semiconductor doping; silicon; PMOSFET gate; Si:Ar; Si:N; boron penetration; doping process; dual-gate technologies; fabrication technologies; impurity doping; logic-embedded DRAMs; multiple-thickness gate oxide; self-aligned thermal oxidation; Argon; Boron; CMOS technology; CMOSFETs; Doping; Fabrication; Impurities; MOSFET circuits; Nitrogen; Oxidation;
Conference_Titel :
Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-4774-9
DOI :
10.1109/IEDM.1998.746371
