Title :
A new DRAM cell technology using merged process with storage node and memory cell contact for 4 Gb DRAM and beyond
Author :
Yoon-Soo Chun ; Byung-Jun Park ; Gi-Tae Jeong ; Yoo-Sang Hwang ; Kyu-Hyun Lee ; Hong-Sik Jeong ; Tae-Young Jung ; Kinam Kim
Author_Institution :
Technol. Dev., Samsung Electron. Co., Yongin, South Korea
Abstract :
A new DRAM cell scheme using merged process with storage node and memory cell contact called BC is introduced for free alignment tolerance between memory cell contact and storage node. The new cell scheme and conventional COB stacked cell scheme are compared for the misalignment tolerance and photo and etch process issues. The new cell scheme is processed in 0.15 /spl mu/m minimum feature size and its results are described including vertical SEM pictures, capacitance-voltage data, and leakage current. This new cell scheme achieved the requirement of memory cell capacitance of 25 fF/cell in 0.30 /spl mu/m pitched 4 Gb DRAMs.
Keywords :
DRAM chips; capacitance; cellular arrays; etching; leakage currents; memory architecture; 0.15 micron; 4 Gbit; COB stacked cell scheme; DRAM cell technology; alignment tolerance; capacitance-voltage data; cell scheme; etch process issues; feature size; leakage current; memory cell capacitance; memory cell contact; merged process; storage node; vertical SEM pictures; Capacitance-voltage characteristics; Capacitors; Dielectrics; Etching; Fabrication; Leakage current; Lithography; Mass production; Random access memory; Shape;
Conference_Titel :
Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-4774-9
DOI :
10.1109/IEDM.1998.746372
