High quality ultra-thin TiO/sub 2//Si/sub 3/N/sub 4/ gate dielectric for giga scale MOS technology

This paper presents the study of physical and electrical properties of ultra-thin (2.0-3.0 nm EOT) TiO/sub 2//Si/sub 3/N/sub 4/ stack gate dielectrics for future giga scale MOS technology. Both layers of the dielectric stack are deposited by the jet vapor deposition (JVD) process. Our experimental data indicate that the leakage current in the TiO/sub 2//Si/sub 3/N/sub 4/ stack is substantially (several decades) lower than that in single oxide layer of the same equivalent oxide thickness (EOT). These films also exhibit excellent interface quality, dielectric reliability, and MOSFET transistor performance comparable to that of thermal oxide.