Title :
SiON/Ta/sub 2/O/sub 5//TiN gate-stack transistor with 1.8 nm equivalent SiO/sub 2/ thickness
Author :
Donggun Park ; Qiang Lu ; Tsu-Jae King ; Chenming Hu ; Kalnitsky, A. ; Sing-Pin Tay ; Chia-Cheng Cheng
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
SiON/Ta/sub 2/O/sub 5/ stacked gate dielectric exhibits 3-5 orders smaller leakage current than SiO/sub 2/ at 1.8 nm, while the transistor characteristics such as mobility, I/sub d/-V/sub g/, and I/sub d/-V/sub d/, are similar to those of SiO/sub 2/ transistor. N-channel MOSFET with equivalent SiO/sub 2/ thickness down to 1.8 nm (1.4 nm equivalent due to elimination of poly-Si depletion) is demonstrated. Process effects are also studied for optimum process condition.
Keywords :
MOSFET; carrier mobility; dielectric thin films; leakage currents; semiconductor device reliability; silicon compounds; tantalum compounds; titanium compounds; 1.8 nm; SiON-Ta/sub 2/O/sub 5/-TiN; equivalent oxide thickness; gate-stack transistor; leakage current; mobility; n-channel MOSFET; optimum process condition; stacked gate dielectric; transistor characteristics; Annealing; Capacitance-voltage characteristics; Dielectric substrates; Electrodes; Leakage current; MOSFET circuits; Permittivity; Tin; Tunneling; Voltage;
Conference_Titel :
Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-4774-9
DOI :
10.1109/IEDM.1998.746379
