Integration technology of polymetal (W/WSiN/Poly-Si) dual gate CMOS for 1 Gbit DRAMs and beyond

Author

Hiura, Y. ; Azuma, A. ; Nakajima, K. ; Akasaka, Y. ; Miyano, K. ; Nitta, H. ; Honjo, A. ; Tsuchida, K. ; Toyoshima, Y. ; Suguro, K. ; Kohyama, Y.

Author_Institution

ULSI Device Eng. Lab., Toshiba Corp., Yokohama, Japan

fYear

1998

fDate

6-9 Dec. 1998

Firstpage

389

Lastpage

392

Abstract

Integration technology of low resistance word line and scaled CMOSFETs for 1 Gbit DRAMs and beyond is proposed. Polymetal (W/WSiN/Poly-Si) word lines and dual gate CMOS FETs with oxynitride gate dielectric were introduced to the 8F/sup 2/ DRAM cell technology. Low sheet resistance of 4.5 /spl Omega///spl square/ word line with 40 nm thick W and high performance dual gate 0.18 /spl mu/m CMOS were successfully integrated without any constraint.

Keywords

CMOS memory circuits; DRAM chips; integrated circuit metallisation; silicon compounds; tungsten; tungsten compounds; 0.18 micron; 1 Gbit; CMOSFET; DRAM cell; W-WSiN-Si; integration technology; oxynitride dielectric; polymetal W/WSiN/poly-Si dual gate; sheet resistance; word line; Boron; CMOS process; CMOS technology; CMOSFETs; Circuits; Delay lines; Dielectric films; Random access memory; Silicon compounds; Ultra large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-4774-9

Type

conf

DOI

10.1109/IEDM.1998.746381

Filename

746381