Design of 12bit 100MHz Sample and Hold circuit for pipeline ADC

Author

Hao, Zheng ; Xiangning, Fan ; Yutao, Sun

Author_Institution

Inst. of RF- & OE-ICs, Southeast Univ., Nanjing, China

fYear

2011

fDate

9-11 Nov. 2011

Firstpage

1

Lastpage

5

Abstract

In this paper, design methods of Sample and Hold (S/H) circuit are discussed and gm/id method in OTA (Operational Transconductance Amplifiers) design is applied. Based upon the discussion, circuit design develops from the signal modeling, which would make circuit design concisely and easily. This work is elaborated in details by TSMC 0.18μm CMOS process. Folding telescope structure is applied for main OTA design, with two gain-boost OPAMPs, in order to achieve high gain and high GBW. In this paper, both main OTA and gain-boost OPAMP are design in gm/id method, and obtain circuit parameters from interpolated data simulated by H-Spice and MATLAB. Post-simulation and chip measurement results show that the S/H circuit performs well.

Keywords

CMOS digital integrated circuits; VHF amplifiers; analogue-digital conversion; integrated circuit design; operational amplifiers; sample and hold circuits; H-Spice; Matlab; OTA design; S-H circuit design methods; TSMC CMOS process; chip measurement; folding telescope structure; frequency 100 MHz; gain-boost OPAMP; interpolated data; operational transconductance amplifiers; pipeline ADC; post-simulation; sample-and-hold circuit; signal modeling; size 0.18 mum; Capacitance; Circuit synthesis; Clocks; Design methodology; Integrated circuit modeling; MATLAB; Transistors; Flip-around S/H; Gain-boost folding telescope OTA; Slew rate; gm/id method;

fLanguage

English

Publisher

ieee

Conference_Titel

Wireless Communications and Signal Processing (WCSP), 2011 International Conference on

Conference_Location

Nanjing

Print_ISBN

978-1-4577-1009-4

Electronic_ISBN

978-1-4577-1008-7

Type

conf

DOI

10.1109/WCSP.2011.6096709

Filename

6096709