DSDPC: Delay signatures at different process corners based hardware trojan detection technique for FPGAs

In applications such as nuclear power plant, space and military, safety critical systems play an important role, where security is one of the crucial design parameters. Similar to software Trojans (virus), Hardware Trojans (HT) are raising security concerns in recent years. HTs are malicious additions or modifications to existing circuit elements which are implemented either as always on or triggered only under certain conditions, to disable functionality, reduce reliability and leak valuable information from the integrated chip. In this paper, we consider the scenario of HTs inserted in field programmable gate array (FPGA) devices during field operating conditions and propose a delay signature based HT detection technique. Static timing analysis is performed to measure the delay signatures of original netlist with that of netlist extracted from field configuration bit file. Since the results of electronic design automation tools are repetitive, we compare both the delay signatures and any deviation will indicate that configuration bit file/ netlist file of the original design is altered. To increase the detection efficiency, we perform static timing analysis at various process corners such as slow, typical and fast corners (at different voltage and temperature combinations) which allows us to measure the best and worst circuit delay values. Using this property, we performed simulations with Xilinx ISE tool by targeting standard benchmark circuits on Xilinx device. Experimental results reflected the difference in delay signatures if configuration bit file is tampered with in the field. The delay difference between with and without HT circuit is enhanced from slow to fast process corner, which in turn increased the HT detection efficiency.