Title :
Accurate characterization of electron and hole inversion-layer capacitance and its impact on low voltage operation of scaled MOSFETs
Author :
Takagi, S. ; Takayanagi-Takagi, M. ; Toriumi, A.
Author_Institution :
Adv. Semicond. Devices Res. Lab., Toshiba Corp., Yokohama, Japan
Abstract :
The influence of inversion-layer capacitance (C/sub inv/) on supply voltage (V/sub dd/) of n- and p-MOSFETs is quantitatively examined. Hole C/sub inv/ is experimentally evaluated in addition to electron C/sub inv/. It is found that the degradation of gate capacitance for holes due to C/sub inv/, is more severe than that for electrons. Self-consistent calculation under a simple valence band model represents the experimental hole C/sub inv/, quite well. It is demonstrated that additional band bending of a Si substrate due to C/sub inv/ becomes a dominant factor to limit the lowering of V/sub dd/ for CMOS with ultra-thin gate oxides. The operation at V/sub dd/ lower than 0.6 V is quite difficult even with effective T/sub OX/ less than 1 nm.
Keywords :
CMOS integrated circuits; MOSFET; capacitance; carrier density; integrated circuit measurement; inversion layers; semiconductor device measurement; semiconductor device models; CMOSFETs; Si; Si substrate; band bending; characterization; electron inversion-layer capacitance; gate capacitance; hole inversion-layer capacitance; low voltage operation; n-MOSFETs; p-MOSFETs; scaled MOSFETs; supply voltage; ultra-thin gate oxides; valence band model; Capacitance; Charge carrier processes; Degradation; Laboratories; Low voltage; MOSFET circuits; Semiconductor device modeling; Semiconductor devices; Substrates; Ultra large scale integration;
Conference_Titel :
Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-4774-9
DOI :
10.1109/IEDM.1998.746434
