High-performance sub-0.08 /spl mu/m CMOS with dual gate oxide and 9.7 ps inverter delay

Author

Hargrove, M. ; Crowder, S. ; Nowak, E. ; Logan, R. ; Han, L.K. ; Ng, H. ; Ray, A. ; Sinitsky, D. ; Smeys, P. ; Guarin, F. ; Oberschmidt, J. ; Crabbe, E. ; Yee, D. ; Su, L.

Author_Institution

IBM Corp., Hopewell Junction, NY, USA

fYear

1998

fDate

6-9 Dec. 1998

Firstpage

627

Lastpage

630

Abstract

We report a high-performance CMOS operating at 1.5 V with 11.9 ps nominal inverter delay at 0.06/0.08/spl mu/m L/sub eff/ for NMOS and PMOS. Both NMOS and PMOS devices, with 3.6 nm inversion T/sub ox/, have the best current drive reported to date at fixed I/sub off/. Low-Vt NMOS/PMOS achieved with compensation and with no degradation in short-channel behavior result in nominal 9.7 ps inverter delay. These devices are incorporated in a 0.18 /spl mu/m technology that offers a 4.2 /spl mu/m/sup 2/ SRAM cell and dual gate oxide for interfacing to 2.5 V.

Keywords

CMOS digital integrated circuits; CMOS memory circuits; SRAM chips; delays; high-speed integrated circuits; integrated circuit design; integrated circuit technology; 0.06 micron; 0.08 micron; 1.5 V; 11.9 ps; 9.7 ps; NMOS devices; PMOS devices; SRAM cell; current drive; deep submicron CMOS; dual gate oxide; inverter delay; short-channel behavior; Circuits; Degradation; Delay; Hot carriers; Implants; Inverters; Latches; MOS devices; Random access memory; Research and development;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-4774-9

Type

conf

DOI

10.1109/IEDM.1998.746436

Filename

746436