Straddle-gate transistor: changing MOSFET channel length between off- and on-state towards achieving tunneling-defined limit of field-effect

Some of the well-recognized constraints in the scaling of the MOSFET are: (a) random-dopants that lead to a large variance in threshold voltage, (b) oxide tunneling that leads to an increase in gate current, and hence strand-by power as well as a reduction in reliability through the increase in carrier flux, (c) limits to the magnitude and shallowness of doping that can be achieved in the source and the drain regions and that lead to poorer sub-threshold swing and higher conductance through electrostatics. The objective of this work is to point out that (a) removal of random dopant effects through removal of channel doping leaves a variance in threshold voltage that is related to lateral fluctuations in the contact region, (b) constant stand-by power density scaling leads to a constraint of 1.5-2.0 nm in oxide thickness for the gate, and (c) the shallow doping regions can be effectively replaced by inversion regions. The straddle-gate transistor, a pentode-like structure, incorporates these ideas together with that of a back-plane structure to achieve an /spl sim/10 nm length scale, where field-effect still dominates, and where the fundamental constraint of source-to-drain tunneling through silicon is restrained by modulating the effective channel length of the device between the on-state and the off-state. At least theoretically, it achieves this length scale within the constraints of power and density, but at the expense of smaller speed improvements with scaling.