Title :
All perovskite capacitor (APEC) technology for (Ba,Sr)TiO/sub 3/ capacitor scaling toward 0.10 /spl mu/m stacked DRAMs
Author :
Hieda, K. ; Eguchi, K. ; Fukushima, N. ; Aoyama, T. ; Natori, K. ; Kiyotoshi, M. ; Yamazaki, S. ; Izuha, M. ; Niwa, S. ; Fukuzumi, Y. ; Ishibashi, Y. ; Kohyama, Y. ; Arikado, T. ; Okumura, K.
Author_Institution :
Microelectron. Eng. Lab., Toshiba Corp., Kawasaki, Japan
Abstract :
All perovskite Capacitor (APEC) technology is proposed to achieve (Ba,Sr)TiO/sub 3/ (BST) capacitor scaling toward 0.10 /spl mu/m DRAM generation. A conductive perovskite-oxide (polycrystalline SrRuO/sub 3/ (SRO)) electrode is introduced as a bottom and a top electrode of BST capacitor. Advantages of APEC technology are low leakage current and less damage to hydrogen-annealing. A new BST-CVD tool with a good film uniformity is also developed to realize a BST film thickness decrease. Both APEC and the new BST-CVD tool are found to be a promising technology for future BST capacitors scaling.
Keywords :
DRAM chips; barium compounds; capacitors; strontium compounds; (Ba,Sr)TiO/sub 3/ capacitor; 0.10 micron; BST film; BaSrTiO/sub 3/; CVD tool; SrRuO/sub 3/; all perovskite capacitor technology; conductive perovskite oxide electrode; hydrogen annealing; leakage current; polycrystalline SRO; stacked DRAM; Binary search trees; Capacitors; Conducting materials; Dielectric materials; Electrodes; Geometry; High-K gate dielectrics; Lattices; Leakage current; Random access memory;
Conference_Titel :
Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-4774-9
DOI :
10.1109/IEDM.1998.746478
