Interconnect design strategy: structures, repeaters and materials toward 0.1 /spl mu/m ULSIs with a giga-hertz clock operation

With the interconnect analysis using the LSI performance prediction model, the local and global line structures are optimized from 0.18 to 0.1 /spl mu/m generations. The chip size enlargement with the wider global line pitch and the inserted repeaters is calculated. It is clear that both low-p and low-k materials are necessary to restrain the chip size enlargement in 0.1 /spl mu/m generation.