DocumentCode :
2575381
Title :
High-speed LMS equalizer for spread spectrum system based on FPGA
Author :
Liu, Bingchao ; Fang, Li ; Li, Daoben
Author_Institution :
Sch. of Inf. & Commun. Eng., Beijing Univ. of Posts & Telecommun., Beijing, China
fYear :
2011
fDate :
9-11 Nov. 2011
Firstpage :
1
Lastpage :
3
Abstract :
To confront the ISI caused by multipath in spread spectrum system,we proposed a hardware architecture of LMS equalizer based on FPGA using parallel processing, which greatly increased the number of iterations in a limited period, and accelerated the convergence of the algorithm. At the same time, the multiplier and the divider was optimized by using the internal hardware multiplier. Simulation results proved that the scheme almost had the same performance compared with the software result with high speed and less hardware consumption.
Keywords :
convergence of numerical methods; field programmable gate arrays; intersymbol interference; iterative methods; least mean squares methods; multipath channels; parallel processing; spread spectrum communication; FPGA; convergence algorithm; field programmable gate array; hardware architecture; high-speed LMS equalizer; internal hardware multiplier; intersymbol interference; least mean square equalizer; multipath channel; parallel processing; spread spectrum system; Algorithm design and analysis; Covariance matrix; Equalizers; Field programmable gate arrays; Hardware; Least squares approximation; Parallel processing; field programmable gate array(FPGA); least mean square(LMS); parallel processing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Wireless Communications and Signal Processing (WCSP), 2011 International Conference on
Conference_Location :
Nanjing
Print_ISBN :
978-1-4577-1009-4
Electronic_ISBN :
978-1-4577-1008-7
Type :
conf
DOI :
10.1109/WCSP.2011.6096798
Filename :
6096798
Link To Document :
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