DocumentCode
2575519
Title
Transistor matching in analog CMOS applications
Author
Pelgrom, M.J.M. ; Tuinhout, H.P. ; Vertregt, M.
Author_Institution
Phillips Res. Labs., Eindhoven, Netherlands
fYear
1998
fDate
6-9 Dec. 1998
Firstpage
915
Lastpage
918
Abstract
This paper gives an overview of MOSFET mismatch effects that form a performance/yield limitation for many designs. After a general description of (mis)matching, a comparison over past and future process generations is presented. The application of the matching model in CAD and analog circuit design is discussed. Mismatch effects gain importance as critical dimensions and CMOS power supply voltages decrease.
Keywords
CMOS analogue integrated circuits; MOSFET; circuit CAD; integrated circuit design; CAD; CMOS analog circuit; MOSFET mismatch; design; transistor matching; Analog circuits; Analog-digital conversion; Clocks; Design automation; Doping; Laboratories; MOSFET circuits; Multiplexing; Neodymium; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International
Conference_Location
San Francisco, CA, USA
ISSN
0163-1918
Print_ISBN
0-7803-4774-9
Type
conf
DOI
10.1109/IEDM.1998.746503
Filename
746503
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