Title :
Hot carrier reliability considerations in the integration of dual gate oxide transistor process on a sub-0.25 /spl mu/m CMOS technology for embedded applications
Author :
Bhat, N. ; Chen, P. ; Tsui, P. ; Das, A. ; Foisy, M. ; Shiho, Y. ; Higman, J. ; Nguyen, J.-Y. ; Gonzales, S. ; Collins, S. ; Workman, D.
Author_Institution :
Networking & Comput. Syst. Group, Motorola Inc., Austin, TX, USA
Abstract :
The competing effects of the well (super steep versus uniform channel) and the source/drain (LDD) structures are analyzed on the hot carrier degradation of 90 /spl Aring/, 3.3V I/O transistor integrated on a 0.25 /spl mu/m, 1.8 V technology with a high performance 35 /spl Aring/, 1.8 V core transistor. The cost vs. reliability trade offs in the dual gate oxide integration are discussed.
Keywords :
CMOS integrated circuits; hot carriers; integrated circuit reliability; integrated circuit technology; 0.25 micron; 1.8 V; 3.3 V; CMOS technology; LDD MOSFET; dual gate oxide transistor; embedded applications; hot carrier degradation; process integration; reliability; source/drain extension; super steep channel retrograde well; uniform channel retrograde well; CMOS process; CMOS technology; Computer networks; Costs; Degradation; Embedded computing; Hot carriers; Implants; Intelligent networks; Voltage;
Conference_Titel :
Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-4774-9
DOI :
10.1109/IEDM.1998.746507
