DocumentCode
2575643
Title
Device design methodology to optimize low-frequency noise in advanced SOI CMOS technology for RF ICs
Author
Ying-Che Tseng ; Huang, W.M. ; Mendiciono, M. ; Ngo, D. ; Ilderem, V. ; Woo, J.C.S.
Author_Institution
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
fYear
1998
fDate
6-9 Dec. 1998
Firstpage
949
Lastpage
952
Abstract
This paper reports on a comprehensive study of low-frequency (LF) noise in surface-channel dual-poly SOI CMOS-FETs. A new understanding of the pre-kink and post-kink excess noise mechanisms as well as the impact of this excess noise on RF ICs are presented.
Keywords
CMOS integrated circuits; UHF integrated circuits; integrated circuit noise; silicon-on-insulator; RF ICs; advanced SOI CMOS technology; low-frequency noise; post-kink excess noise mechanism; pre-kink excess noise mechanism; surface-channel dual-poly CMOSFETs; 1f noise; CMOS technology; Crosstalk; Design methodology; Design optimization; Integrated circuit noise; Low-frequency noise; MOS devices; MOSFETs; Radio frequency;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International
Conference_Location
San Francisco, CA, USA
ISSN
0163-1918
Print_ISBN
0-7803-4774-9
Type
conf
DOI
10.1109/IEDM.1998.746511
Filename
746511
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