A novel 4.6F/sup 2/ NOR cell technology with lightly doped source (LDS) junction for high density flash memories

Author

Jonghan Kim ; Jeong-Hyuk Choi ; Yong-Ju Choi ; Hun-Kyu Lee ; Kyeong-Tae Kim ; Yun-Seung Shin

Author_Institution

Memory Div., Samsung Electron. Co. Ltd., Kyungki, South Korea

fYear

1998

fDate

6-9 Dec. 1998

Firstpage

979

Lastpage

982

Abstract

We have reported a 4.6F/sup 2/ NOR cell with a gate length of 0.3 /spl mu/m. The lightly doped source (LDS) junction is adopted to extend the effective channel length. The word line and source line pitch are significantly decreased with the self-aligned contact processing and W-pad source interconnection. Moreover, the LDS NOR cell shows the improved retention capability and the reduced oxide trapping.

Keywords

CMOS memory circuits; cellular arrays; flash memories; integrated circuit interconnections; 0.3 micron; NOR cell technology; gate length; high density flash memories; lightly doped source junction; oxide trapping; pad source interconnection; retention capability; self-aligned contact processing; source line pitch; word line pitch; CMOS process; Channel hot electron injection; Contact resistance; Electric breakdown; Electron traps; Etching; Fabrication; Flash memory; Silicon compounds; Tungsten;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-4774-9

Type

conf

DOI

10.1109/IEDM.1998.746518

Filename

746518